rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a switched capacitor voltage converter with regulated output ADP3603* ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram 8 spd s1 snd s2 s n d b s3 s n d 7 3 v in c p c p + 1 s4 2 v out gnd osc clock gen 4 sd feedback control loop 5 v sense general description the ADP3603 switched capacitor voltage converter provides a regulated output voltage with minimum voltage loss and re- quires a minimum number of external components. in addition, the a dp3603 does not require the use of an inductor. the ADP3603 prov ides up to 50 ma of output current with 3% output accuracy. the internal oscillator runs at 240 khz nominal frequency which produces an output switching frequency of 120 khz, allowing the use of small charge pump and filter capacitors. the ADP3603 is primarily designed for use as a high fre- quency negative voltage regulator/inverter. the output voltages of the a dp3603 can range from C1.2 v to C4.0 v, nominally C3.0 v. for other output voltages, contact the factory. the ADP3603 dissipates less than 150 mw of power and fea- tures fast shutdown mode capability (<5 ms) that also drops the quiescent current to 1.4 ma (typ). for a higher output current (120 ma) version, see the adp3604. * patent pending. features fully regulated output high output current: 50 ma 120 ma version (adp3604) is also available outstanding precision: 6 3% output accuracy input voltage range: +4.5 v to +6.0 v output voltage: C3.0 v (regulated) high switching frequency: 120 khz (240 khz internal oscillator) shutdown capability small outline 8-pin soic package applications voltage inverters negative voltage regulators computer peripherals and add-on cards portable instruments battery powered devices pagers and radio control receivers disk drives mobile phones pin configuration 8-pin soic (so-8) 1 2 3 4 8 7 6 5 top view (not to scale) nc = no connect ADP3603 c p + v sense nc v out v in gnd c p shutdown ADP3603 8 7 3 c2 4.7? ? 1 4 shutdown 0 off on c1 4.7? ? v in +4.5 ?+6v v out ?.0v c3 4.7? ? 2 5 v sense note c2: sprague, 293d105x0010b2w c1, c3: tokin, 1e105zy5uc205f ? for best performance 10? is recommended figure 1. typical application circuit
pin description pin function 1c p +, pump capacitor positive input. 2 ground. 3c p C, pump capacitor negative input. 4 shutdown, logic level shutdown pin. application of a logic low to this pin will place the regulator in normal operation. the device will be put into shutdown mode with the shutdown pin pulled to v in . in shutdown mode the charge pump is turned off. connect to ground for normal operation. 5v sense , output voltage sense line. this is used to im- prove load regulation performance by eliminating ir drop on the output traces. see application section for more detail. for normal operation, connect pin 5 to v out (pin 7). 6 nc, no internal electrical connection. 7v out, output pin. regulated negative output voltage. connect a low esr capacitor between this pin and de- vice gnd. 8v in, positive supply input when 4.5 v v in 6 v. con- nect a low-esr bypass capacitor between this pin and the device ground pin. parameter symbol condition min typ max units operating supply range v s 4.5 5 6 v supply current i s 2.4 3 ma C40 c < t a < +85 c 2.5 3.5 ma shutdown mode 1.4 2 ma C40 c < t a < +85 c 1.5 2.5 ma output output voltage v o i o = 25 ma C3.1 C3 C2.91 v v o i o = 10 ma to 50 ma, 4.5 v < v in < 6 v C3.1 C3 C2.9 v v o i o = 10 ma to 50 ma, 4.5 v < v in < 6 v, 0 c < t a < +70 c C3.12 C3 C2.88 v v o i o = 10 ma to 50 ma, 4.5 v < v in < 6 v, C40 c < t a < +85 c C3.15 C3 C2.85 v load regulation d v o / i o i o = 10 maC60 ma 0.9 mv/ma i o = 10 maC120 ma 1.5 mv/ma output resistance 2 r o 8 w output ripple voltage 3 v ripple c1Cc3 = 10 m f, i load = 80 ma 25 mv c1Cc3 = 10 m f, i load = 120 ma 55 mv switching frequency f s 100 120 130 khz C40 c < t a < +85 c 96 120 140 khz shutdown logic input high v ih 2.4 v input current i ih 1 m a logic input low v il 0.4 v input current i il 1 m a turn-on-time t on figure 1, i l = 120 ma 5 ms turn-off-time t off figure 1, i l = 120 ma 5 ms notes 1 capacitors c1 and c2 used in the test circuit are 10 m f with 0.1 w esr. capacitors with higher esr may reduce output voltage and efficiency. 2 open-loop output resistance. 3 see figure 1 conditions. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. specifications subject to change without notice . rev. 0 C2C ADP3603Cspecifications warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP3603 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (v in = 5.0 v @ t a = +25 8 c, c p = c out = 10 m f unless otherwise noted) absolute maximum ratings 1 (t a = +25 c unless otherwise noted) input voltage (v+ to gnd, gnd to out) . . . . . . . . . +7.5 v output short circuit protection . . . . . . . . . . . . . . . . . . . . 1 sec power dissipation, so-8 . . . . . . . . . . . . . . . . . . . . . . . 660 mw q ja 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 c/w operating temperature range . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 q ja is specified for worst case conditions with device soldered on a circuit board. ordering guide model temperature range package option* ADP3603ar C40 c to +85 c so-8 *so = small outline package.
ADP3603 rev. 0 C3C supply voltage ?volts oscillator frequency ?khz 130 4.0 4.5 8.0 5.0 5.5 6.5 7.0 7.5 6.0 120 110 figure 2. oscillator frequency vs. supply voltage temperature ? 8 c oscillator frequency ?khz 126 112 ?0 85 070 25 124 122 120 118 116 114 figure 5. oscillator frequency vs. temperature supply voltage ?volts supply current ?ma 3.5 0 4.0 4.5 8.0 5.0 5.5 6.5 7.0 7.5 6.0 3.0 2.5 2.0 1.5 1.0 0.5 normal mode shutdown mode figure 8. supply current vs. supply voltage temperature ? 8 c supply current ?ma 3.0 1.5 0 ?0 85 070 25 2.5 2.0 1.0 0.5 normal mode @ v in = 5v shutdown mode @ v in = 5v figure 3. supply current vs. temperature load current ?ma input current ?ma 80 40 0 10 20 70 30 50 60 40 70 60 50 30 20 10 v in = 5v figure 6. average input current vs. load current 100 90 10 0% 5ms 1v 0v ?v figure 9. start-up under full load temperature ? 8 c output voltage ?volts ?.95 ?.02 ?0 85 070 25 ?.96 ?.97 ?.98 ?.99 ?.00 ?.01 i l = 75ma i l = 50ma i l = 25ma i l = 10ma figure 4. output voltage vs. temperature load current ?ma efficiency ?% 70 0 10 20 70 30 40 50 60 60 50 40 30 20 10 v in = 4.5v v in = 5v v in = 6v figure 7. efficiency vs. load current and input voltage 100 90 10 0% 5ms 1v 0v ?v figure 10. enable/disable time under full load
ADP3603 rev. 0 C4C and s2 are turned off as well as s3 and s4 to prevent any overlap. s3 and s4 are turned on during the second phase (see figure 14) and charge stored in the pump capacitor is trans- ferred to the output capacitor. v in s2 c p s1 v out s3 s4 c out figure 14. ADP3603 switch configuration charging the output capacitor during the second phase, the positive terminal of the pump capacitor is connected to ground and the negative terminal is connected to the output, resulting in a voltage inversion at the output terminal. output regulation is done by adjusting the on resistance of the s3 through the feedback control loop. the ADP3603 alternately charges c p to the input voltage when c p is switched in parallel with the input supply, and then trans- fers charge to c out when c p is switched in parallel with c out . switching occurs at 120 khz rate. during the time that c p is charging, the peak current is approximately 2 times the output current. during the time that c p is delivering charge to c out , the supply current drops down to about 2 ma. an input supply bypass capacitor will supply part of the peak input current drawn by the ADP3603, and average out the current drawn from the supply. a minimum input supply bypass capacitor of 1 m f, preferably a low esr capacitor such as tantalum or multi- layer ceramic chip capacitor, is recommended. a large capacitor may be desirable in some cases, for example when the input supply is connected to the ADP3603 through long leads, or when the pulse current drawn by the device might effect other circuitry through supply coupling. the output capacitor, c out , is alternately charged to the c p voltage when c p is switched in parallel with c out . the esr of the c out introduces steps in the v out waveform whenever the charge pump charges c out . this tends to increase v out ripple. ceramic or tantalum capacitors are recommended for c out if minimum ripple is desired. the ADP3603 can operate with a range of capacitors from 1 m f to 100 m f and larger without any stability problems. however, all tested parameters are obtained using 10 m f multilayer ceramic capacitors. in most applications, ir drops due to printed circuit board traces do not present a problem. in this case, v sense is tied to the output at a convenient pcb location not far from the v out . however, if a reduction in ir drops or improvement in load regulation is desired, the sense line can be used to monitor the output voltage at the load. to avoid excessive noise pickup, the v sense line should be as short as possible and away from any noisy line. capacitor selection while the exact values of the c in and c out are not critical, good quality, low esr capacitors such as solid tantalum and multilayer ceramic capacitors are recommended to minimize voltage losses at high currents. for a given load current, factors affecting the output voltage performance are in figure 15: ? pump (c2) and the output (c3) capacitance ? esr of the c2 and c3. application information the ADP3603 uses a charge pump to generate a negative out- put voltage from a positive input supply. to understand the operation of the ADP3603, a review of a basic switch capacitor building block is helpful. f r l v1 v2 c1 c2 ab figure 11. basic switch capacitor circuit in figure 11, when the switch is in the a position, capacitor c1 will be charged to voltage v1. the total charge on c1 will be q1 = c1v1. the switch then moves to the b position, discharging c1 to voltage v2. after this discharge time, the charge on c1 is q2 = c1v2. the amount of charge transferred from the source, v1, to the output, v2, is: d q = q 1 C q 2 = c 1 ( v 1 C v 2) if the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is: i = f d q = f c1 (v1 C v 2) to obtain an equivalent resistance for the switched-capacitor network we can rewrite this equation in terms of voltage and impedance equivalence: i = ( v 1 C v2)/(1/ fc 1) = ( v 1 C v 2)/ r equiv where r equiv is defined as: r equiv = 1/ f c 1 figure 11 equivalent circuit can now be drawn as shown in figure 12. r l v1 v2 c2 r equiv r equiv = 1 fc1 figure 12. basic switch capacitor equivalent circuit theory of operation a switched capacitor principle is used in the ADP3603 to generate a negative voltage from a positive input voltage. an on-board oscillator generates two phase clocks to control a switching network which transfers charge between the storage capacitors. the basic principle behind the voltage inversion scheme is illustrated in figures 13 and 14. v in s2 c p s1 v out s3 s4 c out figure 13. ADP3603 switch configuration charging the pump capacitor during phase one, s1 and s2 are on charging the pump capacitor to the input voltage. before the next phase begins, s1
ADP3603 rev. 0 C5C temperature ? 8 c esr ? w 10 1.0 0.01 ?0 100 050 0.1 aluminum ceramic organic semic tantalum aluminum ceramic organic semic tantalum figure 16. esr vs. temperature table i. alternative capacitor technologies high type life frequency temp size cost aluminum fair fair fair small low electrolytic capacitor multilayer long good poor fair high ceramic capacitor solid above avg avg avg avg tantalum avg capacitor os-con above good good good avg capacitor avg table ii shows a partial list of manufacturers providing low- esr capacitors. table ii. recommended capacitor manufacturers manufacturer capacitor capacitor type sprague 672d, 673d, aluminum electrolytic 674d, 678d sprague 675d, 173d, 199d tantalum nichicon pf & pl aluminum electrolytic mallory tdc & tdl tantalum tokin mlcc multilayer ceramic murata grm multilayer ceramic external output filtering in applications requiring very low power supply ripple and noise, the circuit in figure 17 provides low noise and ripple of less than 2% of the output voltage over the full load current and temperature. since output current is supplied solely by the output capacitor c3 during one-half of the charge-pump cycle, peak-to-peak out- put ripple voltage is calculated by using the following formula: v ripple = i out 2 f pump () c 2 () + i out esr c 2 () in figure 15, output ripple voltage vs. capacitance and various esr are shown. capacitance ?? output ripple ?mv 60 0 090 10 20 30 40 50 60 70 80 50 40 30 20 10 esr c 50ma v out ADP3603 150m w 100m w 50m w figure 15. output ripple voltage (mv) vs. capacitance and esr note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the esr, no significant reduction in v out ripple is achieved by added capacitance. a low esr capacitor has much greater impact on performance for c2 than c3 since current through c2 is twice the c3 cur- rent. there is a voltage drop across c p s esr during the charge as well as during discharges. therefore, the voltage drop due to c2 is about 4 times c2s esr times the load current. the volt- age drop generated by c2s esr combined with the voltage drop due to the output source resistance, determines the maxi- mum available v out , while c3s esr affects the output voltage ripple. when selecting the capacitors, keep in mind that not all manu- facturers guarantee capacitor esr in the range required by the circuit. in general, the capacitors esr is inversely proportional to its physical size, so larger capacitance values and higher volt- age ratings tend to reduce esr. esr is also a function of the operating frequency. when select- ing a capacitor, make sure its value is rated at the circuits operating frequency. the other factor affecting the capacitors performance is temperature. if the circuit has to operate at temperatures significantly different than 25 c, the capacitance and esr values must be carefully selected to adequately com- pensate for the change. various capacitor technologies offer improved performance over temperature, for example, certain tantalum capacitors provide good low-temperature esr but at a higher cost. figure 16 demonstrates the effect temperature has on various capacitors. ADP3603s high internal oscillator frequency per- mits the usage of smaller capacitance for both the pump and the output capacitors.
ADP3603 rev. 0 C6C table iv. recommended components for circuit in figure 18 component manufacturer/type c3 sprague, 293d475x0035d2w c1, c2, c4, c5 tokin, 1e475zy5uc205f l1 coiltronics, ctx32ct-1r0 l2 coiltronics, ctx32ct-100 shutdown mode ADP3603s output can be turned off by utilizing the shutdown pin, pin 4. pulling the shutdown pin high to a ttl/cmos logic compatible level will stop the internal oscillator and turn off the output pass transistor. a digital low level will turn the output on. if the shutdown feature of the device is not used, pin 4 should be tied to the ground pin of the device. maximum output voltage maximum unregulated output voltage can be obtained by con- necting the sense pin to ground instead of the v out pin as shown in figure 19. under this condition, the magnitude of the unregulated output voltage depends on the load current. v out is inversely propor- tional to the load current as shown on the graph in figure 19. load current ?ma ?.0 ?.0 10 40 v out ?volts 20 25 30 ?.0 ADP3603 8 7 3 1 4 v in = 5.0v 2 5 figure 19. maximum unregulated output voltage under light loads, 30 ma < i load , a regulated output voltage between C3.0 v to Cv in v is possible by inserting a resistor be- tween the sense pin and the v out pin as shown in figure 20. the output voltage is approximated using the following formula: v out = C(3 + r /5) where v out is in volts and r is in k w s. load current ?ma ?.0 ?.0 10 40 v out ?volts 20 25 30 ?.0 ADP3603 8 7 3 1 4 v in = 5.0v 2 5 v out r r = 10k v r = 5k v figure 20. maximum regulated output voltage the output current is supplied solely by the output capacitor c3 during one-half of the charge-pump cycle. this introduces a peak-to-peak ripple of: v ripple = i l 2 120 khz c 3 + i l esr c 3 for a nominal f pump of 120 khz (one-half the nominal 240 khz oscillator frequency) and c3 = 10 m f with an esr of 0.15 w , ripple voltage is approximately 30 mv with a 50 ma load current. multilayer ceramic capacitors (mlcc) offer great perfor- mance and small size. using multiple capacitors connected in parallel yields lower esr and a potential saving in cost. lighter loads require proportionally smaller capacitors. to reduce high frequency noise, bypass the output with a 0.1 m f ceramic capacitor. ADP3603 8 7 3 c2 4.7? 1 4 v in +4.5 ?+6v v out ?.0v c3 4.7? 2 5 sense input l1 10? c4 4.7? c1 4.7? figure 17. circuit with improved output ripple & noise voltage table iii. re commended components for circuit in figure 17 component manufacturer/type c2 sprague, 293d475x0035d2w c1, c3, c4 tokin, 1e475zy5u-c205-f l1 coiltronics, ctx32ct external input filtering if the ADP3603 is supplied from a high-impedance source, connect an additional bypass capacitor from v+ to ground. low-esr capacitors of up to 100 m f give best results. place external capacitors close to the supply pins of the device with the ground connection made as close to the device ground as possible. the same ground point should be used for the output bypass capacitor. smaller bypass capacitors can be used in conjunction with a p -lc filter. ADP3603 8 7 3 c3 4.7? 1 4 v in +4.5 ?+6v v out ?.0v c4 4.7? 2 5 sense input l2 10? c5 4.7? c2 4.7? l1 1? c1 4.7? figure 18. circuit with reduced input and output ripple & noise voltage
ADP3603 rev. 0 C7C power dissipation the power dissipation of the ADP3603 circuit must be limited such that the junction temperature of the device does not ex- ceed the maximum junction temperature rating. power is dissipated in two components, power loss due to volt- age drops in the switches, and power loss due to mosfet drive current losses. total power dissipation is calculated: p ? ( v in C | v out |)( i out ) + ( v in )( i s ) where both v in and v out are referred to ground pin of the ADP3603. for example: assuming the worst case conditions, v in = 5.5 v, v out = C2.85 v, and i out = 50 ma, calculated power dissipa- tion is: p ? (5.5 v C|C2.85 v |)(0.05 a ) + (5.5 v )(0.003 a ) = 149 mw this is far below the power dissipation capability of the ADP3603 package which is 660 mw. layout and grounding tips the ADP3603 switches turn on and off very fast. good pc board layout practices will ensure the proper operation of the device. important layout considerations include: use adequate ground and power traces or planes. keep components as close as possible to the device. use short trace lengths from the input and output capacitors to the input and output pins respectively. use single point ground for the device ground pins and the in- put and output capacitors. improper layouts will result in poor load regulation, especially with heavy loads. applications ADP3603 evaluation board layout the ADP3603 evaluation board is a general purpose circuit board. its flexible design allows the user to optimize the circuit performance by external components selection and circuit con- figuration. the circuit board can be configured as a basic charge pump voltage inverter with one pump capacitor and two bypass capacitors or as a more complex circuit with input and output lc filters. pc layout is designed for surface mount components and can be easily configured for through-hole components as well. ADP3603 8 7 3 c3 4.7? 1 4 v in +4.5 ?+6v v out ?.0v c4 4.7? 2 5 sense input l2 10? c5 4.7? c2 4.7? l1 1? c1 4.7? figure 21. ADP3603 evaluation board circuit diagram table v. recommended components for circuit in figure 21 component manufacturer/type c3 sprague, 293d475x0035d2w c1, c2, c4, c5 tokin, 1e475zy5uc205f l1 coiltronics, ctx32ct-1r0 l2 coiltronics, ctx32ct-100 filtered input input output filtered output shdn output gnd figure 22. 8-pin soic layout, wiring connection c2 c1 c4 c5 l1 c3 l2 figure 23. 8-pin soic layout, component placement diagram (1 scale) figure 24. 8 pin-soic layout, component side (1 layout)
ADP3603 rev. 0 C8C c2169C12C9/96 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-pin soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
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